It is distinguished from the so-called static logic by exploiting temporary digital electronics and logic design pdf free download of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high speed digital electronics, particularly computer CPUs.
Dynamic logic circuits are usually faster than static counterparts, and require less surface area, but are more difficult to design. Dynamic logic has a higher toggle rate than static logic but the capacitative loads being toggled are smaller so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e. CMOS or dynamic SOI design.
Dynamic logic is distinguished from so-called static logic in that dynamics logic uses a clock signal in its implementation of combinational logic circuits. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed.
In the context of logic design, the term dynamic logic is more commonly used as compared to clocked logic, as it makes clear the distinction between this type of design and static logic. To additionally confuse the matter, clocked logic is sometimes used as a synonym for sequential logic. This usage is nonstandard and should be avoided. The largest difference between static and dynamic logic is that in dynamic logic, a clock signal is used to evaluate combinational logic.